Reductions in the size and inherent features of semiconductor devices, for example, metal-oxide semiconductor (MOS) devices, have enabled continued improvements in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. In accordance with a design of the MOS device and one of the inherent characteristics thereof, modulating the length of a channel region underlying a gate between a source and a drain of a MOS device alters a resistance associated with the channel region, thereby affecting the performance of the MOS device. More specifically, shortening the length of the channel region reduces a source-to-drain resistance of the MOS device, which, assuming other parameters are maintained relatively constant, may allow for an increase in current flow between the source and drain when a sufficient voltage is applied to the gate of the MOS device.
To further enhance the performance of MOS devices, stresses may be introduced in the channel region of a MOS device to improve its carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an n-type MOS (NMOS) device in a source-to-drain direction (channel length direction) and to induce a compressive stress in the channel region of a p-type MOS (PMOS) device in the channel length direction.
A commonly used method for applying compressive stresses to the channel regions of MOS devices is to form stressed contact etch stop layers (CESL), which apply stresses to the underlying MOS devices. Since the CESLs were existing components of MOS devices, the introduction of the stressed CESLs resulted in little, if any at all, extra manufacturing costs. For NMOS devices, the overlying CESLs need to have inherent tensile stresses, and apply tensile stresses to the channel regions. For PMOS devices, the overlying CESLs need to have inherent compressive stresses, and apply compressive stresses to the channel regions.
CESLs apply a same stress (either tensile or compressive) to the underlying MOS devices from all directions. However, a MOS device may prefer different types of stresses in different directions. For example, PMOS devices prefer compressive stresses in the channel length directions, and tensile stresses in the channel width directions. Therefore, the compressive stresses applied to the channel width directions of the PMOS devices actually degrade the performance of the PMOS devices. A new structure is provided by the present invention to address the customized stress requirements of the MOS devices.